System IP Design Verification Engineer (Sr. Staff-SCI)

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a System IP Design Verification Engineer you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical leadership/individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.

• You architect and build re-usable testbenches right from scratch
• You propose and drive best practices/methodologies/automation that can improve productivity
• You own key features and timely execution of tasks as per milestones
• You create test plans as per spec and present to various stakeholders
• You work with designers to resolve any spec issues
• You create test benches, verification environments, stimulus, tests
• You collaborate with designers to verify the correctness of a design feature, and resolve fails
• You develop assertions, checkers, covergroups, and System Verilog constraints
• You analyze and debug, root causing functional fails from regressions
• You analyze code and functional coverage results, performing gap analysis
• You work with SoC team to debug functional fails during IP bringup and feature execution
• You collaborate with Physical Design teams, running and debugging gate-level simulations
• You collaborate with Performance Verification teams to help with co-sim TB bringup
• You handle bringup power-aware verification with UPF
• You help with Silicon bringup and root causing fails
• You mentor junior team members, work independently, and are a team player

Skills and Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD
• 15+ years industry experience in a Design Verification role
• Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure
• Experience with System Verilog, UVM or equivalent
• Knowledge of ARM protocols or equivalent protocols – CHI, AXI, ACElite, APB
• Experience with Git version control, Unix/Perl/Python scripting
• Combined experience with coherent interconnect, caches, and LPDDR memory controllers is highly preferred
• Formal verification skills are a plus
• Good written and verbal communication skills

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.