Sr. DFT/MBIST Engineer

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

The Senior DFT/MBIST Engineer is responsible for designing and implementing Memory Built-in Self Test (MBIST) solutions across a variety of digital IP (CPU/GPU) and SOC projects. You will work closely with stakeholders to define MBIST architectures, create implementation specifications, implement MBIST solutions in RTL and generate high quality patterns. You will also be responsible for ensuring high test-coverage, minimizing test-time, and exploring tools/methods to improve execution efficiency. Finally, you will collaborate closely with SOC and Product/Test Engineering teams to quickly resolve silicon issues. This position is located in Austin, TX.

• You understand SOC requirements and project milestones to define a DFT architecture that optimally balances coverage, test-time, and execution.
• You create a detailed implementation spec that documents MBIST architecture details such as SOC-level interface, clock design, memory load/dump debug interface, Power on MBIST self-test, among others.
• You close on the spec with stakeholders including DFX/RTL/SOC/STA/PD teams.
• You implement MBIST: RTL insertion, LINT, timing-constraints, MBIST pattern generation, logic to maximize scan coverage of memory, and interface with MBIST.
• You implement MBIST with power and physical considerations in mind.
• You drive towards DFX excellence: improving test-coverage, minimizing test-time, and exploring tools/methods that improve execution efficiency.
• You build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve silicon issues including test-escapes and yield loss.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a PhD
• 10+ years of DFT/MBIST expertise encompassing multiple tapeouts for digital IP (CPU/GPU) and/or SOC projects.
• Demonstrated ability to architect MBIST solutions from scratch on at least 1 project, and to create detailed specifications that can be used as a blueprint for implementation.
• Detailed understanding of MBIST test requirements and implementation.
• Experience with Siemens MBIST solutions/Tessent MemoryBIST or comparable is required.
• Strong familiarity with RTL coding & STA, with working knowledge of Physical Design.
• Exposure to advanced approaches such as hierarchical DFT.
• Strong post-silicon experience in debugging silicon behavior and test-escape issues.
• Familiarity with multi-voltage and multi-clocking domain implementation is a plus.
• Ability to solve difficult problems with creative solutions or analysis.
• Crisp written and oral communication skills including working with global stakeholders.
• Thrives in a fast-paced environment: i.e., yearly project tapeouts.

Our Team

We’re strengthening our team of talented individuals with diverse skill sets to build a technology roadmap and deliver market-leading GPU. Our Xclipse GPU is the first mobile GPU with ray tracing technology that enables console-level graphic for Samsung Galaxy smartphones. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Our Physical Design group is part of the larger Design Implementation team at SARC/ACL. The fast-paced environment here provides us opportunities to learn different areas of design implementation and diversifying our technical expertise. We take p