Memory Performance Architect – Intern

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Memory Architect – Intern

Location – US (San Jose/Austin)

Summary

We are looking for an intern to help build performance models, perform architectural tradeoff analysis and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. An architecture foundation and hardware modelling experience (C++/Python) is desired.

Responsibilities

• Develop cycle-level C++/SystemC performance models and analysis of hardware features, applications, benchmarks, and use cases
• Analyze memory subsystem-level architectural trade-offs (throughput, latency, power, hardware cost) across different scenarios
• Develop synthetic memory traffic/traces that are representative of real-world SoC components (CPU, GPU, DSP, NoC, etc)
• Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks
• Correlate performance models to match RTL across configurations and traffic conditions
• Work with Memory Architects to understand feature requirements and evaluate architectural choices and tradeoffs

Required Skills

• Currently pursuing a MS or PhD in electrical/Computer Engineering or equivalent
• Strong coding skills in C++/SystemC, python and similar programming languages
• Basic understanding of performance principles, e.g. Amdahl’s Law, Queuing Theory, throughput/latency tradeoffs

Additional Skills

• Experience in architecture analysis and hardware modeling (functional or performance) and simulator development skills
• Understanding RTL, analyzing waveforms
• Understanding of memory protocols and timing – DDR4, DDR5, LP4, LP5
• Experience with industry standard or academic performance simulators at any level – Memory, SoC, CPU models
• Experience using performance benchmarks
• Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and QoS

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