Senior Staff Engineer, ASIC Design

Please Note:

To provide the best candidate experience with our high application volumes, we limit applications to a total of 10 over 6 months. 

Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Do

The APL (Advanced Processor Lab) is one of the research team's of SAIT (Samsung Advanced Institute of Technology) which is Samsung‘s R&D hub, established as the incubator for cutting-edge technologies. SAIT’s mission has covered various research areas from AI applications/algorithms research, neuromorphic processor, domain-specific accelerators to new materials, quantum computing, and super computer system.

APL is committed to shaping the future of CPU processor and SoC architecture for the most demanding applications of the future like AI and HPC. We are building the foundation of processors and the related platform which are applied to various business targets of Samsung in the future. 

We are seeking a highly skilled ASIC Design Engineer with expertise in backend design and experience in CPU/GPU/DSP RTL design to join our dynamic engineering team. The ideal candidate will have experience in the complete ASIC design flow, from RTL coding to backend physical design and tape out, with a strong understanding of CPU architectures and performance optimization. Experience with prototyping platforms and FPGAs is strong plus. 

Job ID: 42314

•  Develop and implement RTL for CPU cores and related IPs.
• Work closely with frontend and backend teams to ensure optimal design closure, including timing, area, and power optimizations.
• Collaborate on the development of micro-architecture specifications for CPU components.
• Conduct synthesis, STA (Static Timing Analysis), DFT (Design for Test), and other validation tasks as required.
• Perform backend tasks, including place and route (PR), physical design closure, and tape out.
• Ensure the design meets performance, area, power, and reliability targets.
• Participate in the design and verification of complex digital IP blocks, integrating them into the overall Sock
• Interface with verification, DFT, and software teams to resolve design issues and ensure smooth handoffs between design phases.
• Work with prototyping platforms and FPGAs to validate designs before moving to silicon.

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What You Bring

• Bachelors in Electrical/Computer Engineer with 15 years of relevant industry experience, or Masters in Electrical/Computer Engineer with 13 years or PhD in Electrical/Computer Engineer with 8 years preferred.
• 10+ years of experience in ASIC design with hands-on expertise in both frontend (RTL) and backend design processes.
• Experience in ASIC physical design flows, including synthesis, place and route, clock tree synthesis, and timing closure.
• Experience in CPU/GPU/DSP RTL design, including knowledge of instruction sets (ARM, RISC-V, x86), out-of-order pipeline design, and performance tuning.
• Proficiency in tools such as Synopsys (Design Compiler, IC Compiler), Cadence, or Mentor Graphics.
•  In-depth knowledge of Static Timing Analysis (STA), timing closure, and power optimization techniques.
• Experience with prototyping platforms (such as Zebu or FPGAs), including experience with FPGA-based validation and design iteration, will be a plus.
• Strong problem-solving skills and ability to work in a fast-paced geo-diverse environment

Preferred Skills:

• Experience with high performance, high frequency, low-power design methodologies.
• Experience with Verilog, SystemVerilog, SystemC, Chisel.
• Familiarity with scripting languages such as Python, for design automation.
• Knowledge of high-performance computing and multicore systems.
• Experience with memory hierarchy, multi-level cache design, and interconnects like AXI/ACE/CHI/Tile Link or similar bus protocols.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.