Sr Physical Design Engineer

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About this opportunity:

ASIC Physical Design Engineer
Build It From Scratch | 5G Silicon | Ericsson Austin, TX
This is an on-site, hybrid position and not open to remote work.

A clean sheet with your name on it.
Most engineers spend their careers inheriting someone else's flows, someone else's tool choices, someone else's methodology decisions. This is not that job.

This is the ground floor. The blank canvas. The moment where the decisions you make become the foundation that everything else gets built on. If you've ever sat in a design review thinking "I would have done this completely differently" — here's your chance to prove it.

Why Austin. Why Now.
Austin has become one of the most important semiconductor cities in the world — and Ericsson has planted a flag here. You'll be working in a city that's become a magnet for serious silicon talent, with a team that collaborates globally with engineering counterparts in Sweden, while keeping its roots and its energy firmly in Central Texas.

This isn't a satellite office running someone else's playbook. This is a primary design site.

What You're Actually Building
Ericsson's Radio and Baseband products run on our ASICs. Full stop. These chips are the backbone of 5G networks deployed around the world — and the complexity, power targets, performance requirements, and advanced process node technology involved means this work will push you in ways that most design roles simply won't.

You'll work across IP and SOC levels, partner with engineers in Austin and Sweden, and be part of Ericsson's vertical development capability — meaning you're not just designing a chip, you're part of an integrated engineering ecosystem that optimizes every layer of the stack to deliver something the market can't match.

What You'll Own:
Define the physical design flow — tools, methods, and processes — from the ground up
Drive design execution at both the IP and SOC level, with flexibility to shift focus as program needs evolve
Partner with design, CAD, and cross-disciplinary teams to bring complex ASIC physical designs to life
Help build the team itself — recruiting, interviewing, onboarding, and mentoring the engineers who come after you
Work hands-on with advanced process node technology and push methodology further on every tape-out
Own problem resolution and execution — not just participation

What You'll Bring:
10+ years of physical design experience in SOC, IP, or ASIC environments
BS in EE or CE (minimum)
Deep expertise in one or more of: PPA optimization, RTL checks & synthesis, floorplanning & routing, power & timing closure, or signoff
Solid working knowledge of back-end disciplines — EMIR, DFM, DFT, power grid analysis
A genuine team orientation — you mentor, you collaborate, you elevate the people around you
Proven ability to drive execution and close hard problems under real program pressure.
SystemVerilog knowledge
Semi-custom design experience
Strong scripting skills

Ericsson has been making bold decisions for over a century. That's not marketing — it's the reason 5G networks on multiple continents run on our silicon. When you join this team in Austin, you're joining a company that gives engineers the ownership, the tools, and the global reach to build things that actually matter.