Senior Staff Engineer, Pre-silicon Emulation

Please Note:

To provide the best candidate experience with our high application volumes, we limit applications to a total of 10 over 6 months. 

Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Do

The Advanced Controller Development (ACD) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash.  ACD’s vision is to solve key problems of Cloud & Data center by developing the new technology for storage (SSD) controller. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

We are looking for a dynamic, self-motivated Staff Pre- silicon emulation Engineer.

As an emulation engineer, you will be responsible for involve working on Emulator platforms for Advanced Memory controllers to improve capabilities and debug issues. Responsibilities include bringing up the emulation platform for ACD projects and developing monitors and checkers for the emulation platform. The role includes debugging emulation performance and area issues, also developing and maintaining the emulation environment.

Location: Hybrid, working onsite at our San Jose, CA or Folsom, CA offices 3 days a week, with the flexibility to work remotely the remainder of your time.

Job ID: 42182

• Enable digital design teams to meet targets by closely supporting and troubleshooting Emulation flow usage
• Technical knowledge and proficiency working with at least one industry-standard HW emulator platform: Palladium, Zebu, Veloce
• Own and maintain emulation infrastructure
• Be able to understand SystemVerilog RTL design and test environment to port over to Emulation platform.
• Own and maintain chip level emulation models for validating different subsystems
• Work with vendors on hardware and tool issues on a need basis
• Enhance emulation methodology for robustness, test throughput, portability and debuggability
• Work cross functional with simulation, firmware and software test team to validate the chip pre-silicon. Support SW test bring up and debug on hardware emulator, collaborate with hardware design team to triage and fix design issues.
• Leverage understanding of simulation-based design verification flows to help emulation test-planning and execution
• Work cross functional with simulation, firmware and software test team to repro failures seen in real silicon on the emulation
• Be able to independently troubleshoot digital tool flow usage and deploy solutions
• Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments
• The ability to manage Linux environments is also required.
• Ability to work with internal and external tool developers to implement enhancements to support a highly efficient workflow

What You Bring

• Bachelors in Electrical, Computer Science or related with 15+ years of experience or Masters in Electrical, Computer Science or related Science with 13+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 10+ years of Industry Experience Preferred.
• Emulation experience on any of the emulation platforms: Palladium, Zebu or Veloce.
• Experience with emulation compile flow, wave dump & triggers, waveform debug, running tests
• Experience writing scripts in Perl or Python
• Exposure to Makefile or other build flows
• Experience with waveform debug tools such as Verdi/SimVision
• Good understanding of Verilog and SystemVerilog RTL design.
• Exposure to synthesizable SystemVerilog/Verilog code and SVAs
• Strong communication skills and a team player
• Strong scripting and automation skills using Tcl/Perl/Python
• Experience implementing digital logic designs in emulation methods
• Experience in ASIC design flow
• Experience in memory controller and related IP level and/or SOC level verifica