Senior Product Engineer, Silicon

Minimum qualifications:

• Bachelors degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
  
• 5 years of experience with Very-large-scale integration (VLSI) technologies, product and test engineering, and semiconductor processing.
  
• Experience in ATE or System-Level testings using AdvanTest or UFlex systems.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
  
• Experience with Machine Learning (ML) based statistical automation to improve test cost, coverage and quality in Semiconductor Industry
  
• Experience with process technology, and design and testing Data analysis: wafer sort, final test.
  
• Experience with SERDES, PCIe, DDR and Mixed-Signal circuits such as ADC, DAC, PLL, LDO and their performance measurements.
  
• Experience with Design for test (DFT) techniques and structural tests (e.g., Scan/ATPG, JTAG and memory BIST) and familiarity with testing sensors such as PVT sensors, Temp sensors etc.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role you will help develop and deploy a comprehensive test solution using Automatic Test Equipment (ATE) for high volume manufacturing at FABs, OSATs etc. that meets final product's performance and power specifications.You will help integrate SoC technologies into devices and facilitate ATE manufacturing testing of SoC to validate performance and screen out devices. You will own all aspects of testing and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs.You will demonstrate an understanding of IC flows, wafer processing, testing, qualification and failure analysis is expected. You will work with various groups to develop digital and mixed signal tests, automation methodologies, develop or support internal tools for test program generation, vector tracking, test program release, etc. You will also work on releasing cost effective production test solutions into mass production.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Perform SoC (AI centric) Product Specifications and DFT Architecture reviews and generate NPI characterization/test/manufacturing plans.
  
• Support Test Hardware (HW) design (probe card, Load board) requirements, ATE/SLT Test program review, and strive test coverage to achieve <250 DPPM. 
  
• Perform Die/Package level bring-ups, troubleshoot different failure modes and help resolve issues by collaborating with cross-functional teams. 
  
• Perform IDS, Vmin and Key KPI characterization and systems correlation, conduct reviews, generate reports to meet product's AI performance and power targets.
  
• Manage NPI and Manufacturing RMAs to achieve Turn Around Times (TATs) and provide lot dispositions.