Principal Engineer - HBM SOC Physical Design - TPG

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary:

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

As an HBM SOC Physical Design Engineer, you will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful. You will apply your deep understanding of SOC Structural Design, high-speed interface design, high-performance computing architectures, and 2.5D & 3D package integration to understand and analyze bottlenecks and propose innovative architectures to target best-in-class performance, power, cost, reliability and quality for Micron’s HBM product portfolio.

In HBM HIG (High Bandwidth Memory – Heterogenous Integration Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, simulation, testing, debugging and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only while the Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) of HBM is the most challenging due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting.

What’s Encouraged Daily:

• Completing various tasks in the netlist to GDSII implementation for partition(s), meeting schedule, and design goals.

• Collaborating with the Architect, Front End Design, and CAD teams to deliver best-in-class designs.

• Assisting Front End Design and Integration Engineers with SRAM/RF specification and synthesis design constraints.

• Resolving and improving design and flow issues related to physical design, identifying potential solutions, and working with CAD teams as needed.

• Being proactive in identifying and flagging quality issues, performance problems, and opportunities to reduce power consumption, whether in Architecture, Microarchitecture, RTL, or Circuits.

• Debugging and identifying root causes and solutions for netlist timing issues or post-silicon timing issues.

How To Qualify:

• In-depth technical expertise in one or more areas: Physical Synthesis, Floor-Planning, Place and Route, Power Grid, Clock Tree Synthesis, Static Timing Analysis for Partition Level and Full Chip Level Timing Closure, SRAM Compilers, Physical Design Verification (DRC/LVS), Formal Equivalence Verification (FEV), ATPG.

• Proficiency in writing TCL with demonstrated experience in using TCL with one or more Physical Design Tools.

• A solid understanding of Unified Power Format (UPF) for describing power intent.

• Excellent knowledge of Synthesis Design Constraints and Static Timing Analysis.

• Excellent understanding of clocking concepts, including asynchronous crossings and structures used to synchronize clock domain crossings.

• Good understanding of computer architecture concepts, including SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB, etc.

• 7+ years of relevant job/skill-related experience.

• Experience delivering highly technical solutions.