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Sr. Staff Design Engineer - SOC
MIPSUnited Statesfull_timeVerifiedPosted 21 Oct 2024
About the role
We are seeking an experienced Sr. Staff Design Engineerfor SoC. Responsible for leading and owning RTL development of one or more modules of a high-performance SoC and integration of the SoC. The candidate will be responsible for all aspects of the design including Integration, Performance, Power, and Area.
At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!
More about us: MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.
Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.
You will:
- Drive the micro-architecture and design multiple blocks of the SoC Ips or other control IPs.
- Perform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications.
- Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals.
- Perform Functional verification support and assist in the design verification strategy
- Assist with the verification of RTL design performance goals
- Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power
Ideally, you’ll have:
- Hands-on knowledge of high-performance microcontroller or Micro-processor architectures.
- Experience with simulators and waveform debugging tools.
- Knowledge of logic design principles along with timing and power implications.
- Knowledge of System Verilog, UVM, UPF and parametrized designs and configurable designs.
- Experience with major EDA tool vendor tools like Synopsys/Cadence/Tessent is desirable. Hands on knowledge of Synopsys Tools is preferable.
- In depth and hands on knowledge of bus architecture like AXI/AHB/equivalent protocols and various peripherals/CPU core integration.
- Excellent analytical and problem-solving skills.
- Masters or Bachelor’swith 8-11 years of experience, PhD + 5-7 years of work experience
A plus if you have:
- Experience with designing RISC-V, ARM, and/or MIPS CPU
- Understanding of low-power architecture techniques.
- Experience using a scripting language such as Perl or Python.
At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!
More about us: MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.
Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.
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