Director, Silicon Design Verification

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. 

 As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.  

We are looking for a Director, Silicon Design Verification Manager to join the team.

Responsibilities

• Build, hire, and mentor a team of talented engineers, supporting their career growth and professional development. 
• Lead a pre-silicon verification team for the development of custom IP and Subsystem (SS) components with focus on architectural and micro-architectural based functions and features. 
• Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP- or SS-level verification. 
• Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. 
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments. 
• Collaborate across verification teams on vertical and horizontal reuse of components. 
• Define and implement functional coverage and drive coverage closure. 
• Triage and debug testbench, simulation, and emulation fails. 
• Write makefiles and scripts for verification infrastructure. 
• Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. 
• Provide technical leadership through mentorship and strong teamwork.

Qualifications

Required/Minimum Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Equivalent Experience.
• 7+ years of experience in design verification with a proven track record of delivering high performance IP, SS or SOC testbenches. 
• 5+ years of experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM) 
• 5+ years of experience debugging Register Transfer Level (RTL) designs as well as simulation and/or