Physical Design Engineer

About usWe are searching for talented individuals who are driven to tackle the most ambitious goal of our time - building the computer hardware that enables the development of safe artificial general intelligence. See more at fathomradiant.co/aboutus
In our people, we above all value kindness, a scout mindset, a focus on improvement, and prioritising to get the right things done. We aim to help build one of the most transformative technologies in the world, with massive social and ethical implications. We think this makes representation even more important, and we are actively striving to have a range of diverse perspectives on our team.
This roleWe’re searching for a Physical Design Engineer with a strong first principles approach for our cutting-edge ASICs used to accelerate machine learning computation in data centers. You will collaborate closely with a team of experts, including RTL Design Engineers, Mixed-Signal IC Design Engineers, and specialists in SerDes and high-speed data communication, to bring cutting-edge computing technologies from concept to reality. Your expertise will ensure the physical integrity of our designs, optimizing them for performance, power, and area (PPA), and driving the innovation that leads to groundbreaking computing solutions.
This role is open to remote from anywhere in the world, but we have strong preference towards availability in US and / or Central Europe timezones.
This role aims for multiple hires in different seniority levels.

Areas of contribution

• Lead the physical implementation of complex SoCs, including floorplanning, placement, routing, timing closure, formal verification, low power design and clock distribution
• Work closely with the RTL and Mixed-Signal design teams to ensure seamless integration of digital and analog components, with a special focus on SerDes and high-speed interfaces.
• Drive and execute design quality and convergence for digital ASIC from RTL to GDS
• Close sign-off checks, interface with industry foundries and GDS delivery
• Work extensively with cross functional teams to guide architecture with physical design constraints
• Establish tool flows and drive vendors to achieve milestones
• Develop and implement methodologies and scripts for automation of physical design processes, enhancing efficiency and accuracy.

Requirements (necessary skills for this role):

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Industry tape-out experience
• 5+ years of experience in the physical design of complex SoCs, with a proven track record in leading projects to successful tapeout.
• Expertise in the use of industry-standard physical design tools and methodologies, such as Cadence Innovus, Synopsys IC Compiler, and Mentor Graphics Calibre.
• Strong understanding of the entire physical design flow, from netlist handoff to GDSII generation, including DRC, LVS, and ERC checks.
• Experience with timing closure and optimization techniques, power grid and clock tree synthesis, and post-layout simulation.
• Understanding of deep sub-micron design issues and solutions
• Extensive Perl/Tcl scripting experience
• Ability to work collaboratively in a team environment, with excellent communication skills and the capacity to engage effectively with cross-disciplinary teams.

Nice-to-haves (we will prioritize candidates that also have these skills):

• Experience with physical design in advanced process nodes (7nm, 5nm, or below).
• Experience with Python for design automation.
• Familiarity with high-speed communication protocols and standards, enhancing the ability to integrate these systems within SoC designs.

For all roles, we target market salaries, with an additional benefits package. Our comprehensive benefits include startup equity and medical expenses coverage (including extra coverage for employees with a family). The salary in our offers are determined based on years of experience, living expenses (for remote roles) and our internal salaries.