Senior Design Verification Engineer

<h2>Short Description</h2> <p>Are you in search for a new challenge? Are you equipped with forward looking spirit and experienced in digital design flows and tools?</p> <p>Take the opportunity and join us as a Senior Design Verification Engineer:</p> <p> </p> <p>We offer you:</p> <ul> <li>Competitive Salary &amp; Benefits;</li> <li>Respect for your private life and your choices;</li> <li>All tools required for high performance in your field;</li> <li>Responsible approach, long-term commitments, and stability.</li> </ul> <p> </p> <h2>Qualifications</h2> <ul> <li>6+ years experience</li> <li>Sound basics of system Verilog, and good experience in constrained Random and Coverage Driven Verification with UVM/OVM</li> <li>Experience in creating any UVC components or sequences is must</li> <li>Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above.</li> <li>Should be comfortable in updating the existing verification environment for feature updates. (bring-up/Architect UVM based Test bench from Scratch is a strong plus)</li> <li>EDA simulation/debugging tools agnostic</li> <li>Good knowledge of Perl/TCL/Python scripting.</li> <li>Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile</li> </ul> <h2>Job Responsibilities</h2> <ul> <li>Own verification of IP’s and SoC’s in prototype and SoC design environment;</li> <li>Establish functional and performance benchmarks;</li> <li>Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;</li> <li>IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.</li> </ul>