Sr Manager Design Development Technical Leadership, HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Design Development Technical Lead (DDTL) is accountable for predictable, timely delivery of HBM design achievements across the design phase of the product lifecycle. This role serves as the single‑threaded technical program owner for HBM Design execution, coordinating across DRAM, base die, test vehicles, interposers, IP, and foundries(internal and external).

Operating within Micron’s Heterogeneous Integration Group (HIG), the DDTL leads cross‑functional execution, manages design dependencies and risks, owns change control, and represents HBM Design in PDT and executive forums to ensure schedule, cost, quality, and product objectives are met

Responsibilities

Design Program Ownership

• Own end‑to‑end execution of on schedule delivery of HBM design achievements, ensuring alignment across DRAM, base die, test chips, PTVs, interposers, and sustaining designs.
• Be the primary design representative in PDT and executive reviews.
• Define and manage cross‑functional dependencies across all collaborators
• Lead execution governance, including DDTL Syncs and Design Program Reviews (DPRs), providing clear executive‑level status, risks, and decision asks.
• Own and operate formal Change Control Board (CCB) processes, ensuring disciplined POR management, cost/schedule awareness, and traceability.
• Maintain a comprehensive design risk register. Proactively identify risks, lead mitigation workgroups, define checkpoints, and bring up issues through governance forums as required.
• Capture and institutionalize lessons learned to improve future program execution.
• Drive early engagement during architecture and design phases to enable shift‑left risk mitigation.
• Lead initiatives to optimize die size, DFM, yield, cost, power, and manufacturing efficiency.
• Ensure HBM products meet best‑in‑class targets for performance, power, quality, reliability, and cost.

Foundry, IP & External Partner Leadership

• Lead design‑phase engagement with external foundries and IP providers, identifying and resolving execution dependencies.
• Own IP forecasting, selection, and prioritization, aligning technical needs with budget and roadmap constraints.
• Lead design contractor, IP vendor, and procurement engagements supporting design execution.

Finance, Budgeting & Cost Ownership

• Own design‑phase financial accountability for the HBM portfolio.
• Develop IP cost projections, track actuals, manage approvals, and drive prioritization in alignment with design and business objectives.
• Manage mask cost planning and execution for test vehicles, test chips, and live die across TSMC and UMC nodes, ensuring cost transparency and schedule alignment.

Roadmap Ownership & Communication

• Serve as the program‑level central owner of the HBM design roadmap.
• Maintain, integrate, and communicate roadmap updates across Design, PDT, and executive collaborators.

Customer & Executive Interface

• Capture customer requirements and schedules for customized HBM products and ensure execution alignment.
• Partner with Business, Finance, and Product teams to align design execution with roadmap and market priorities.
• Provide concise, data-driven executive communications, advancing critical issues when necessary.

Process, Metrics & Continuous Improvement

• Define, standardize, and deploy program management tools and dashboards (e.g., Jira, status templates, CCB workflows).
• Monitor and report key execution metrics, driving corrective actions and continuous improvement.
• Develop scalable business processes to support increasing portfolio complexity and design scope.

Qualifications

• Understanding of custom and digital design flows and the full SoC/DRAM development lifecycle.
• Demonstrated ability to lead large, cross‑functional technical programs through influence and execution rigor.
• Experience working with foundries, IP vendors, and ecosyst