Senior HBM Foundry Interface Design Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary: 

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. 

In our hybrid role, you will be part of HBM Design Architecture team and provide technology support for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical subject matter experts collaborating closely with a global team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to execute to a common goal of ensuring our future HBM roadmap is successful. You will interface between the internal design teams and external foundries (and internal Technology development teams) to understand and analyze technology/design bottlenecks and help design architects to propose innovative architectures to target best-in-class performance, power, cost, reliability, and quality for Micron’s HBM product portfolio. 

Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment, and groundbreaking technology while rapidly growing your abilities. 

In HBM DEG (High Bandwidth Memory, DRAM Engineering Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most ambitious due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting. 

 Responsibilities include but are not limited to  

• Focused, self-motivated semiconductor foundry interface engineer providing strategic and technical leadership across the semiconductor industry involving wafer foundries and fabless design houses. 

• Use foundry technology process design kits (PDKs) of advanced FinFET and GAA nodes to come up with design guidelines for power/performance optimization. 

• Study and analyze Foundry Technology to provide guidelines to design team to improve power/performance/area and reliability. 

• Participate in new architecture development for upcoming and future HBM base Die design through Design Technology Co-optimization involving std cells and BEOL options. 

• Define Reliability specifications for DRAM and Base Die through cross-functional