Sr. Engineer, SoC Design Verification

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Tenstorrent is seeking a Senior SoC Design Verification Engineer who will focus on pre-silicon verification of PCIe logic in advanced AI SoCs, driving coverage of connectivity, compliance, interoperability, and bring-up features critical to silicon success.</p> <p>This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA.</p> <p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p>&nbsp;</p> <h3>Who You Are</h3> <ul> <li>Deeply curious about PCIe architecture, link behavior, and subsystem verification.</li> <li>Expert in UVM and verification of PCIe controller, PHY-facing logic, LTSSM, and protocol flows.</li> <li>Comfortable working with PCIe Gen4/Gen5 features, compliance concepts, and advanced verification automation.</li> <li>Proactive, detail-oriented, and thrives in cross-functional technical discussions.</li> <li>Ideally familiar with tools similar to CocoTB.</li> </ul> <h3>What We Need</h3> <ul> <li>Develop and own verification environments for PCIe logic across AI chiplets and SoCs.</li> <li>Write, refine, and execute test scenarios for link training, enumeration, power management, error handling, and data movement features.</li> <li>Analyze coverage gaps, debug failures, and collaborate closely with architecture, RTL, and system teams.</li> <li>Automate flows for PCIe protocol testing, interoperability validation, and integrate AI productivity tools.</li> </ul> <h3>What You Will Learn</h3> <ul> <li>In-depth PCIe verification using cutting-edge workflows, tooling, and scripting.</li> <li>Integration of pre-silicon PCIe verification with silicon bring-up and platform validation strategies.</li> <li>How AI-driven automation reshapes modern DV workflows.</li> <li>Exposure to high-performance, system-level connectivity verification in advanced SoC designs.</li> </ul>