Sr. ASIC Design Engineer

Sr. ASIC Design Engineer

  

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

   

Job Family Definition:

HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches.  

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.  

As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow. 

Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.  

Responsibilities: 

• You will start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements. 

• You will implement the design using Verilog or System Verilog  

• Write functional coverage/SVA to help verification catch corner case bugs. 

• You will work with the Physical Design team for optimal floorplan and timing closure. You will identify and fix timing in RTL to meet the frequency target.  

• Work with the Verification team to make sure your block is fully validated.  

• You will have opportunities to improve leadership skills by providing mentoring/guidance to new college-grad engineers and interns.  

  

Recommended skills 

• Bachelor’s degree in Electrical Engineering required