Senior Technologist, Hardware Development Engineering -

Company Description

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

We are seeking an Expert-level Hardware Engineer who is equally strong in board-level hardware design and ASIC interface / integration (I/O, package, power integrity, DFT/test, analog, and signal integrity). This is a hands-on role for a recognized subject matter expertise in delivering complex hardware from concept through production, including deep lab bring-up and root-cause complex issues, able to debug across silicon, package, and board.

Qualifications

Must have Experience for the following

• Professional hardware engineering experience.
• Proven ownership of multiple complex programs through the full lifecycle: architecture → design → build → bring-up → debug → qualification → production ramp → sustaining.
• Demonstrated, hands-on experience spanning both:
  • Board/system hardware design (schematic ownership, layout partnership, bring-up, debug, standards compliance, manufacturing support)
  • ASIC I/O and integration (I/O architecture decisions, package/substrate considerations, PI/SI co-design, tape-out support, DFT/test hooks)

Cutting-Edge High-Speed Interfaces (Must Have)

• Hands-on experience integrating and debugging leading-edge Ethernet and PCIe interfaces, including:
  • 100G/200G Ethernet PAM4 transceivers (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
  • PCIe Gen 6 (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
• Demonstrated ability to design and simulate high-speed links across die/ASIC package/PCB/connectors/cabling, balancing SI/PI/EMI and manufacturing constraints.

FPGA Board Design — Must Have

• Proven experience designing complex boards using cutting-edge FPGAs (e.g., high-end families with high-speed transceivers), including:

  • Power architecture and sequencing for FPGA multi-rail systems

  • High-speed transceiver channel design, with associated reference clock design,
  • reset/boot/strap
  • Bring-up and debug using vendor tools, link training, PRBS/IBERT-style testing, and lab correlation
• Ownership of FPGA-based platform bring-up from first power-on through high-speed link validation and system integration.
• AMD FPGA Knowledge preferred

Board-Level Design (Hands-On)

• Expert schematic design and review for high-complexity boards (compute/networking/accelerator-class or equivalent).
• Strong experience with:
  • Multi-rail power distribution networks (frequency domain impedance control, sequencing, fault handling)
  • High-speed interfaces (DDR, PCIe, Ethernet/SerDes-based links, USB, I2C, SPI, MIPI—based on product needs)
  • Controlled impedance trace design (understanding manufacturing and cost tradeoffs)
  • Clocking/reset/fault tolerant architectures and debug access design
  • General analog circuit design
• Proven partnership with layout teams to define and enforce:
  • Stackups, reference planes, return paths, via design and strategy, routing constraints
  • Differential pair controlled impedance routing, channel constraints, connector strategy, manufacturability

Signal Integrity (SI) & Power Integrity (PI) Across Die / Package / Board

• SI design experience: Insertion loss, retu