Job Details:

Job Description:

At Altera, we’re pioneering the future of programmable compute. As a standalone FPGA company backed by decades of innovation, we deliver industry-leading programmable logic, software, and IP to power the next wave of cloud, edge, AI, and networking solutions. Our mission is to make programmable technology easier to design and deploy, enabling customers to accelerate innovation at scale.

We are looking for a Senior Principal Engineer, Design Engineering to join our world-class engineering team. In this role, you will own the architecture, microarchitecture, and RTL design of high-performance subsystems that power next-generation FPGAs, SmartNICs, DPUs, and compute platforms. You will drive technical direction, performance closure, and design quality across global teams—partnering with architecture, verification, and customer engineering groups to deliver first-pass production silicon.

Responsibilities:

• Define and develop microarchitecture specifications for complex subsystems including host interfaces, DMA engines, scatter-gather engines, and interconnects.

• Lead RTL design and coding for critical datapath and control logic, ensuring performance, area, and power targets are met.

• Partner with verification leads to establish test plans, review environments, and accelerate debug and coverage closure.

• Drive performance definition, benchmarking, and optimization in both pre-silicon simulations and post-silicon systems.

• Collaborate with architects, product planning, and hyperscaler customers to align requirements with deliverables.

• Lead design reviews and technical sign-off across multiple projects, ensuring rigorous standards and methodology adoption.

• Guide cross-functional collaboration with software and driver teams for system-level performance alignment.

• Innovate in area and power optimization strategies through advanced design techniques.

Leadership & Influence:

• Act as a strategic technical leader, shaping design engineering direction across multiple programs and influencing product roadmaps.

• Provide thought leadership in microarchitecture and RTL design, setting standards and best practices adopted across the organization.

• Mentor, coach, and grow the next generation of design leaders, ensuring continuity of expertise and leadership in core technologies.

• Represent Altera in technical forums, standards committees, and customer engagements, demonstrating deep expertise in PCIe, CXL, and host interface design.

• Champion methodology innovation across design, verification, and performance analysis to drive faster delivery and higher silicon quality.

• Drive cross-functional alignment at the executive level, ensuring architecture, design, and verification strategies are cohesive and effective under aggressive schedules.

Salary Range:

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$221.5K - $326.3K USD

Qualifications:

Minimum Qualifications:

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field.

• 20+ years of experience in ASIC/SoC design engineering.

• Proven expertise in microarchitecture specification and RTL design of large-scale subsystems and IPs.

• Strong knowledge of PCIe (Gen1–6), CXL, SR-IOV, ATS/PRI, and host interface protocols.

• Hands-on experience with Verilog/SystemVerilog RTL coding, linting, and synthesis-aware design.

• Demonstrated success in performance benchmarking, simulation, and post-silicon validation.

• Track record of leading teams to deliver production-quality silicon for networking, storage, or compute solutions.

Preferred Qualifications:

• Master’s degree in Electrical/Computer Engineering or related field.

• Deep experience with SmartNICs, DPUs, NVMe, and compute accelerators.

• Knowledge of networking protocols such as Ethernet (100G+), RoCE, iWARP, and TCP/IP offloads.

• Strong customer-collaboration experience with hyperscaler or custom silicon projects.

• Holder of multiple U.S. patents in microarchitecture, I/O, or system performance.

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