Senior Analog Layout Engineer

About the job you’re considering
•    10+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies
•    Experience with and knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.)
•    Experience leading complex layout macros during the full design cycle from floorplan analysis to completion of physical design verification
•    Great understanding of CAD flows and tools related to analog/mixed-signal layout design
•    Experience crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc.
•    High level of proficiency in custom, as well as standard cell-based, floor planning and hierarchical layout assembly
•    Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance
•    Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems
•    High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports
•    Knowledge of CADENCE or MENTOR GRAPHICS layout tools.
•    Excellent interpersonal skills and able to work with remote teams    

Your role

•    Lead layout team in completing complex layout for analog/mixed-signal circuits in deep submicron CMOS technologies
•    Be a great role model, by inspiring and motivating team, and Establishing Effective Organizational Structure and Communication Protocols. Able to Delegate and Empower team along with Effective Time Management.
•    Working with the circuit designer or Layout-Lead to plan/schedule work and negotiate any layout trade-offs as needed
•    Reviewing and analyzing floorplans and complex circuits with circuit designers
•    Running complete set of design verification tools available on AMS blocks
•    Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout
•    Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements

Your skills and experience

Synopsys/Cadence Analog Layout Tools (Preference: 5)
Virtuoso (Preference: 5)
Calibre (Preference:5)
Python (Preference:2)

Life at Capgemini

Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:

• Flexible work
• Healthcare including dental, vision, mental health, and well-being programs
• Financial well-being programs such as 401(k) and Employee Share Ownership Plan
• Paid time off and paid holidays
• Paid parental leave
• Family building benefits like adoption assistance, surrogacy, and cryopreservation
• Social well-being benefits like subsidized back-up child/elder care and tutoring
• Mentoring, coaching and learning programs
• Employee Resource Groups
• Disaster Relief

About Capgemini Engineering

World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has 65,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive