Runtime Software Engineer, Staff

d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in early 2024. We are poised to meet the energy and performance demands of these Large Language Models. The company has 70+ employees across Silicon Valley, Sydney and Bengaluru.

Location:

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.

The role: Runtime Software Engineer, Staff

What you will do:

d-Matrix is developing an AI inference processor for accelerating the inference of NLP, Vision, and Recommendation workloads, in a data center environment. The architecture uses an in-memory compute processor subsystems, with a mix of fixed-point and floating-point data types in both dense and sparse matrix processing modes. During the seed round, the company has developed a 6nm CMOS test chip, and validated the architecture using real inference workloads compiled from PyTorch.

The position is a Runtime SW Engineer to work on the architecture and development, and validation of the functionality and efficiency  of firmware/ software which is executed on System on Chip’s multiple processors, and low level drivers and system programs which hosts this System on Chip.

In this role, you will be largely responsible for all aspects of runtime performance of the silicon product. You will architect, document, and develop the runtime firmware that executes in the various on-chip multi-core CPU subsystems. This firmware will be controlling all aspects of the AI subsystems in the chip and will be architected to maximize the utilization of the hardware. Measures of success will be overall AI hardware utilization, minimizing communication bottlenecks and maximizing on-chip memory utilization.

You will bring the software up on FPGA platforms (that contain images of the embedded CPU subsystems) and debug it using JTAG-connected IDE. You will develop a firmware solution that can be developed and tested ahead of the availability of the AI subsystem hardware.

You will be responsible for determining the delivery schedule, and ensuring the software meets d-Matrix coding and methodology guidelines. You will collaborate with the hardware teams (to interpret the hardware specifications, and suggest changes that improve utilization and throughput, and-or reduce power). You will collaborate with other members of the SW team (located in AU and US), the SW quality & Test team (US and India), as well as the HW verification team (to assist with SoC-level DV simulations and emulation).

You will be developing and debugging code on the FPGA-based systems containing CPU subsystems and SystemC models of the AI subsystems and SoC You will also be involved in porting the software to a “big iron” emulation system (e.g. Veloce, Palladium) containing the final RTL.

You will also be closely involved in the bring up of the software on the AI subsystem hardware and validating silicon and software performance.

What you will bring:

• BS / MS Preferred degree in Computer Science, Computer Engineering or similar.

• Experience with multi-threaded C programming on multi-core CPUs running an RTOS in both AMP and SMP configurations.

• Understanding of methods used to synchronize many-core and many-CPU architectures.

• Managing static resources without an MMU.

• Zephyr OS experience is an advantage.

• Experience with PIC programming and developing interrupt service routines.

• Knowledge of bootloaders and Linux device drivers is an advantage.

• Ability to interpret HW-centric data sheets and register definitions, to determine how to best program the architecture.

• Ability to work with HW design teams at both the early definition phase and during development.

• Experience with FPGA based development and system emulators is an advantage.

• Ability to work with SW Architecture teams and propose considered feedback on SW architecture.

• Knowledge of assembly language programming of pipelined RISC architecture processors.

• Runtime FW debugging on target hardware using IDE via JTAG

• Experience with current SW development methodologies including Git, Kanban, Sprints, Jenkins, Jira (or similar).

• Experienc