Principal Engineer, High‑Speed RTL Design

Key Responsibilities 

High‑Speed RTL Design & Implementation 

• Design and implement timing‑critical RTL blocks, including:  

• Control and sequencing FSMs 

• Power‑up, shutdown, and mode‑transition logic 

• Register banks and configuration logic 

• Telemetry and monitoring datapath 

• Develop RTL with attention to latency, deterministic behavior, race‑free logic, and metastability avoidance. 

 Nanometer‑Process‑Aware RTL Coding 

• Write RTL that is robust to:  

• Tight setup and hold margins 

• Clock skew and uncertainty 

• Multi‑cycle and false‑path constraints 

• Process, voltage, and temperature (PVT) variation 

• Ensure RTL is clean for synthesis, static timing analysis, and ECO cycles in sophisticated technology nodes. 

Clocking, Reset & Power‑Aware Logic 

• Implement and review clock‑domain crossings (CDC) using proven synchronization techniques. 

• Design reset and initialization logic to ensure predictable system startup and recovery. 

• Support power‑aware and mode‑dependent behavior as the need arises by system operation. 

Integration & Debug 

• Integrate RTL blocks into larger subsystems or top‑level designs, resolving:  

• Port‑list mismatches 

• Clock and reset dependencies 

• Mode interaction issues 

• Debug RTL and integration issues using simulation waveforms and tool feedback. 

Verification & Timing Closure Support 

• Work closely with verification engineers to:  

• Clarify design intent and corner cases