Principal Engineer - DFT

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Company Overview</strong></span></p> <p><strong>Ambiq</strong>&nbsp;is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.</p> <p>Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.</p> <p>Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.</p> <p>We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.</p> <p>At Ambiq, we live by five values:&nbsp;<strong>Innovate. Collaborate. Focus. Learn. Achieve.</strong></p> <p>If that's you, join us — the intelligence everywhere revolution starts here.</p> <p>&nbsp;</p></div><p>Ambiq is seeking an experienced&nbsp;<strong>Principal DFT (Design for Testability) Engineer</strong> to lead the architecture, implementation, and continuous improvement of DFT solutions across our ultra-low-power SoC portfolio.</p> <p>This is a highly hands-on technical leadership role for an engineer who can operate across the complete DFT lifecycle—from architecture and RTL integration through scan insertion, ATPG, MBIST, verification, silicon bring-up, and production test. The Principal DFT Engineer will serve as a key technical authority for DFT methodology, working closely with RTL design, verification, physical design, STA, and test engineering teams to ensure Ambiq products meet aggressive testability, quality, yield, power, and manufacturing-cost objectives.</p> <p>The successful candidate will initially be expected to contribute directly to implementation while helping evolve Ambiq's DFT architecture, infrastructure, and methodology across multiple concurrent SoC programs.</p> <h2>Responsibilities</h2> <ul> <li> <p>Lead DFT architecture, implementation, and methodology across complex ultra-low-power SoCs.</p> </li> <li> <p>Own hands-on implementation using <strong>Cadence Genus and Modus Compression</strong>, including low-power scan insertion, compression, ATPG pattern generation, debug, and coverage closure.</p> </li> <li> <p>Defin