Job Details:

Job Description: 

At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define issue scope, plan execution, and innovate competitive solutions to meets customer needs.

This role is to support Physical Verification (DRC/LVS or/and Extraction) for Intel leading edge PDKs. You will perform the PV runs, identify the violation, work with teams to clarify problem root causes, find or/and implement the solutions. Tasks will also include owning/maintaining training documents, user guide, and customer issue support.

As a DEAS (Design Enablement Application and Support) key member, you must have communication skills to interact with customers directly, apply analytical problem-solving capability to identify the key requests, and root-cause the issue in a teamwork environment with DE stakeholders to support and enable customer success.

#DesignEnablement

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 3+ years of experience or MS degree 2+ years of experience or PhD degree with 1+ years of experience in Electrical/Computer Engineering, or related STEM fields.

3+ years of experience in the following:

- Experience with one of the Physical Verification tools like Calibre, ICV or Pegasus, with skill set and knowledge on debugging.
- Intel and/or external foundry process technology knowledge in advance nodes.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, California, Santa Clara, US, Texas, Austin

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$123,419.00-$185,123.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.