Lead Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Understand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification.

Required experience

• Testbench construction and block level UVM verification experience
• Hands-on experience of coverage collection & analysis including
  • Development of functional coverage monitors
  • Integration of functional coverage monitors with a test planning and analysis solution
  • Experience of analyzing and proposing solutions to address functional coverage holes
  • Experience of analyzing and proposing solutions to address code coverage holes
• A good understanding of AMBA bus protocols
• Experience of verification environments including
  • script development
  • source control systems
• Good knowledge of verilog/vhdl/C/C++/Perl/Python.
• Familiarity with ARM/CPU architectures.

Desirable skills and experience

• Good knowledge of some of the protocols: UART, I2C, SPI
• Embedded C code development and debug
• Formal Verification experience
• Cadence verification tool experience

Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new  methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing take up additional responsibilities to contribute to team’s success.

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