Junior Engineer for Korea ISG

1)    Front-End Logic design
-    Hardware design in Verilog HDL
-    Verification with golden model
2)    Back-End design
-    Logic synthesis / Formal verification

1)    Front-End Logic design
-    Hardware design in Verilog HDL
-    Verification with golden model
2)    Back-End design
-    Logic synthesis / Formal verification

-. Bachelor’s degree or above in Semiconductor-related or Electrical/Electronic Engineering
-. Understanding of image sensors is preferred
-. Proficiency in C++ and Python is preferred
-. Strong English communication skills are preferred
-. Meal and transportation expenses will be provided