HBM System Architect

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary:

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

As an HBM System Architect, you will be tasked with conducting in-depth architectural analysis and performance modeling of memory components and systems. Your role will involve identifying potential bottlenecks and proposing design improvements to optimize memory performance. This will necessitate a proven understanding of areas such as DRAM memory subsystems, DRAM controllers, DFI, and industry-standard memory interfaces and protocols. You will be part of a highly multi-functional team of technical guides, collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering, and Business Units to ensure the success of our future HBM roadmap. The seniority level offered will be based on a combination of experience and education.

In HBM DEG (High Bandwidth Memory - DRAM Engineering Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most ambitious due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting.

Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity.

(Disclaimer): While you may not exhibit all of the characteristics/skills listed below today, we are highly interested in a teammate who is motivated to grow in technical breadth and depth. Suppose you are open to learning while being a valued member of a team of best-in-class engineers. In that case, we are determined to help build upon your existing foundation, while rapidly growing your individual and collaborative skills in this exciting and outstanding opportunity.

What’s Encouraged Daily:

• Conduct architectural analysis, performance modeling, and simulations of memory components and/or systems to identify bottlenecks and propose design improvements.

• Perform C++ performance modeling of proposed architectural solutions and features.

• Collaborate with multi-functional teams to develop architectural solutions.

• Analyze and present results meticulously to enable data-specific architecture/design decisions.

How To Qualify:

• BS or MS with 3+ years of relevant Engineering experience, or NCG Ph.D. with related experience

• Experience with memory performance analysis, modeling, and simulation tools (e.g., Ramulator, DRAMSim).

• Experience with GPU/CPU performance analysis, modeling, and simulation tools (e.g., GPGPU, GEM5).

• Excellent C/C++/scripting coding, debugging, and testing skills.

• Good understanding of computer architecture, memory systems, and memory technologies.

What Sets You Apart:

• Solid understanding of memory controller designs, cache coherence protocols, and memory management techniques.

• Familiarity with