Senior ASIC Design Verification Engineer (Hardware)

Company Description

Our Mission

At Palo Alto Networks® everything starts and ends with our mission:

Being the cybersecurity partner of choice, protecting our digital way of life.

Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are.

Our Approach to Work

We lead with flexibility and choice in all of our people programs. We have disrupted the traditional view that all employees have the same needs and wants. We offer personalization and offer our employees the opportunity to choose what works best for them as often as possible - from your wellbeing support to your growth and development, and beyond!

At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work from the office three days per week, leaving two days for choice and flexibility to work where you feel most effective. This setup fosters casual conversations, problem-solving, and trusted relationships. While details may evolve, our goal is to create an environment where innovation thrives, with office-based teams coming together three days a week to collaborate and thrive, together!

Job Description

Your Career

As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability.  You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug.  You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation.

We expect office-based employees to be in the office three days per week, with two days working from where they choose. We believe being together facilitates casual conversations and those magic moments where we can work on issues and ideas informally. These moments build capability and deepen trusted relationships and allow our people to feel safe in taking risks and being disruptive. Like so many companies, we are working through the details and things could change …. but in general if a role is deemed office-based we want our teams to be together four days per week.

Your Impact

• Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification

• Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies

• Develop flows, methodologies, and infrastructure for emulation - Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers

• Define new tools and methodologies to continuously improve quality and velocity

• Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification

Qualifications

Your Experience

• BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred

• Minimum 5 years experience in ASIC design verification

• Demonstrated success in taking multiple ASIC products from concept to mass production

• Expertise in SystemVerilog and UVM

• Technical strength in the following areas is required

  • Defining test plans, including comprehensive adversarial testing

  • Developing rich functional coverage models

  • Creating powerful and scalable test benches

  • Implementing sophisticated self-checking infrastructure with reference models and scoreboards

  • Developing reusable constrained-random tests

  • Debugging failures

  • Closing coverage

• Experience in the following areas is preferred

  • Networking and cyber security

  • Formal property verification

  • Silicon validation - bringup, test, debug, and regression

  • Creating models in Python and C/C++

  • Writing driver code in C

• Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing

• Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status

• Strong leadership, collaboration, and communication skills