Sr. Mixed Signal Semiconductor Design Engineer

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

Organization & Role

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is looking for an enthusiastic candidate for the position of Semiconductor Design Engineer, to design high-speed analog circuits in mixed-signal ASICs for ATE (Automatic Test Equipment) instruments. We are looking for a candidate with CMOS design and layout experience who has successfully taped-out several designs.  

Responsibilities

• Develop detailed circuit specifications for mixed signal circuits
• Conceive circuit architectures and transistor level circuit topologies that satisfy required performance
• Provide guidance for physical implementation (layout) of high-speed circuits
• Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions
• Integration of circuit elements into large analog/mixed signals ASICs
• Participation in the characterization and test of ASICs

Basic Qualifications & Skills

• CMOS FinFET (16nm or lower) design experience is a plus
• Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design – both electrical and physical design
• Desired experience in design of VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high frequency I/Os and/or high frequency CML designs
• Involvement in all phases of multiple IC developments from specification to product introduction
• Familiarity with characterization and modeling of standard and custom logic cells
• Solid understanding of Cadence RTL/STA/SDF gate level verification flows
• Solid understanding of CMOS semiconductor device physics and device modeling
• Solid understanding of thermal effects of various circuit topologies
• Solid understanding of electromagnetic theory
• Solid understanding and experience with IC characterization at high frequencies using high speed sampling oscilloscopes, spectrum analyzers, VNAs, signal sources
• Solid understanding of PDKs
• Proficiency in Verilog or Verilog-A modeling is a plus

Education

• MSEE, or higher preferred, in electrical engineering with 15+ year experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits

 

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