CPU System and Compute Die Architect

Mission 

We are dedicated to transforming industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you’ll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing server-class high performance solutions that are highly optimized for the needs of the server product.  

Position: CPU System and Compute Die Architect  

We are hiring talented engineers for CPU System Architecture focusing on various aspects of CPU System like Interrupt, Timer, address map, coherent and Non-coherent NoC protocols, Debug and RAS (Reliability, Availability, Serviceability) aspects along with understanding of impact of multi-die system for high performance, low power architectures. In this role, you will work with architects and SW teams to conceive of micro-architecture and help with the product definition through early involvement in the product life cycle. 

The ideal candidate will have extensive knowledge of CPU and SoC architecture across various product segment – Datacenter Server, Mobile, Compute and Auto SoCs, including experience in microarchitecture and design of coherent CPU systems. CPU system architecture involves micro-architecture and deployment of data, control and debug features using interconnects, deploying various solutions for RAS and Debug and trace architecture. Strong analytical, problem-solving, and communication skills are essential for excelling in this position. 

Required for this Role:

• MS degree in Computer or Electrical Engineering with 15+ years of CPU and SoC architecture or similar experience. 

• Deep knowledge of microprocessor architecture, with expertise in one or more of the following areas: 

• CPU system features: interconnect protocols, timer synchronization, interrupt controller, configuration access protocols, RAS and safety mechanisms 

• Comprehending compute dies and the complexities involved in designing a CPU with multiple dies along with Die-to-Die channel understanding 

• Power and performance telemetry solutions: Architecture and performance monitoring, telemetry architecture 

• Architecture and Micro-architecture Debug and Trace architecture, scan-dump, and memory dump mechanisms and understanding of various DFx technologies 

• Excellent technical documentation skills, along with strong written and verbal communication abilities 

• Understanding of various Software and Firmware control loops and building system level solutions. 

• Solid understanding of logic design principles, including timing and power implications 

Preferred qualifications 

• MS degree in Computer or Electrical Engineering. 

• Understanding of CPU and cluster architec