Senior SOC Pre-Silicon Verification Engineer- HBM Design

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary:

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

As an HBM SOC Pre-Silicon Verification Engineer, you will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high-speed interface design, high-performance computing architectures, and 2.5D & 3D package integration to understand and analyze bottlenecks and propose innovative architectures to target best-in-class performance, power, cost, reliability and quality for Micron’s HBM product portfolio.

In HBM HIG (High Bandwidth Memory – Heterogenous Integration Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, simulation, testing, debugging and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only while the Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) of HBM is the most challenging due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting.

What’s Encouraged Daily:

• Develop test plans at IP/Subsystem/SOC Level.

• Review architectural specifications to ensure high quality.

• Be efficient and productive in executing project deliverables, whether developing verification environments, creating test plans, writing and running tests, debugging failures, coding assertions and cover points, and modifying tests to hit target coverage.

• Work with IP suppliers to ensure that proper validation collateral is provided.

• Work with customers to understand their validation requirements and provide validation collateral as needed.

• Be proactive in identifying and flagging quality issues, performance problems, and opportunities to reduce power consumption.

• Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures.

• Engage with customers to support issues with current HBM architectures and find opportunities to innovate on future HBM solutions.

How To Qualify:

• Ability to develop validation environments using System Verilog and UVM.

• Ability to write tests using UVM.

• Experience with writing assertions and coverage monitors using SVA.

• Knowledge of Register Description Languages such as SystemRDL and UVM RAL.

• Solid understanding of computer architecture concepts.

• Experience with SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB, etc.

• Experience with scripting languages such as Python.

• 4+ years of relevant job/skill-related experience.

• Experience delivering highly technical solutions.

What Sets You Apart:

• BSEE or greater.

• Proven track record of innovation and problem-solving in building v