Sr. Digital Verification Engineer

Sr. Digital Verification Engineer

Job Summary:

A Senior Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.

MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile and network equipment.

Essential Functions:

• UVM and System Verilog based Digital Verification environment definition and development.

• VIPs standardization, definition, development and documentation.

• Define VIP’s integration into the Project’s Digital Verification environment.

• Digital Verification Metrics definition for RTL and Gate-Level Verification.

• Test Plan definition and development.

• Digital Verification Automation and Scripting.

• Regression’s infrastructure definition, development and management.

• Close interaction with Senior Digital and Analog Designers to develop VIP models.

• Lead and Supervise Digital Verification Tasks of multiple projects and Digital Verification Team.

• Review Digital Verification Metrics and Results of multiple projects.

• Define and design Digital Verification Top-Level Tests.

• Analyze and debug test results, code coverage and functional coverage.

• Digital Verification estimation, planning and scheduling to meet tape-out dates.

Qualifications:

•PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.

•5+ years of strong experience in both RTL and Gate-Level Verification.

•Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.

•Proficient Level in DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.

• Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.

• Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.

• Excellent scripting and automation skills using TCL, Python or C/C++.

• Leadership skills to technically guide the DV Team and mentor Jr. DV Designers.

• Good written/verbal communication skills and strong team work/collaboration.

• Knowledge/Experience with the following is a plus:

             Embedded designs and/or firmware development

             Knowledge of power management industry/applications

             I2C, I3C, SPI, USB, PMBUS

             GITLab

Location: Enschede/ Nijmegen, Netherlands