Physical Design Engineer, Static Timing Analysis

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  
• 5 years of experience in static timing (i.e., to create full chip timing constraints, perform full chip static timing analysis and timing ECO creation).
  
• Experience in working across various physical design areas (i.e., EDA scripting, block level synthesis, floorplanning, place and route, and congestion mitigating utilizing standard EDA tools).
  
• Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.
  

Preferred qualifications:

• 12 years of experience in the domain of physical design and static timing analysis.
  
• Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
  
• Experience in full chip design planning and working with multiple foundries.
  
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
  
• Knowledge of semiconductor device physics and transistor characteristics.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Create complex TCL timing constraints.
• Perform full chip static timing analysis, timing ECO creation, and final timing sign-off for ASIC tape outs.
• Perform block level synthesis, floorplanning, and place and route.
• Utilize Perl, Python, Tcl, and Bash to create flow automation scripts.
• Own and maintain Primetime STA flows.
  

Create complex TCL timing constraints.