Job Details:

Job Description: 

About Intel Foundry Services

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Position Overview

The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.

Key Responsibilities

Physical Verification Support & Issue Resolution

• Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
• Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
• Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations

Technical Content Development & Training

• Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
• Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs
• Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies

Verification Methodology Leadership

• Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)
• Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations
• Drive methodology improvements to streamline customer design workflows and enhance verification productivity

Customer Engagement & Technical Excellence

• Deliver customer-facing technical support with focus on physical verification challenges and solutions
• Support customers through complex verification issues and advanced process technology adoption
• Ensure maximum customer satisfaction through expert guidance and responsive technical support

Core Competencies

• Self-driven and results-oriented with capability to effectively manage multiple complex tasks
• Strong analytical problem-solving skills for complex physical verification challenges
• Effective communication skills with experience in collaboration, active listening, and providing constructive feedback

Qualifications:

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• US Citizenship required
• Ability to obtain a US Government Security Clearance
• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
• 5+ years of experience with advanced CMOS processes (22nm and below)
• 4+ years of combined experience in layout verification and parasitic extraction EDA tools
• 4+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)

Preferred Qualifications

• Active US Government Security Clearance with a minimum of Secret level
• Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
• Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)
• Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools
• Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
• Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
• Experience in providing technical direction to engineering te