Job Details:

Job Description: 

Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.

Qualifications:

Minimum Qualifications:

You must possess a B.S. in Computer Engineering or Electrical Engineering with 2+ years of experience listed below; OR a M.S. in Computer Engineering or Electrical Engineering with 1+ years of experience listed below; OR a PhD in Computer Engineering or Electrical Engineering with emphasis on formal verification in the following areas:

In-depth computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management.

Hands on experience with industry standard formal verification tools such as JasperGold, Questa Formal, VC Formal.

Experience with applying sequential equivalence checking in complex micro-architectures.

Experience with formal abstractions and other complexity reduction techniques. Experience with a hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools.

Experience in assertion writing, checker development, coverage analysis, failure debug, root cause analysis.

Programming experience in at least one language: C/C++, Perl, Python, Ruby, Java, TCL, etc.

Intel or industry experience in pre-silicon verification of CPU cores, including specific areas of technical ownership/expertise relevant to CPUs.

Preferred Qualifications:

Knowledge of Intel Architecture ISA and system architecture, x86 assembly language.

Post-silicon debug and analysis.

Research publications, patent filings, or other evidence of personal technical innovation in validation methodology advancement.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, California, Folsom, US, California, Santa Clara, US, Texas, Austin

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here: