Principal Physical Design Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Design Center Engineering (DCE) Physical Design team at Marvell in Westborough, MA is seeking a Principal Physical Design (PD) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wireless infrastructure—using the latest technology nodes.

Our team leverages cutting-edge EDA tools to solve the complex challenges involved with taking multi-million instance blocks from RTL to GDS-ready and integrating this at the partition and full-chip levels. This role involves close collaboration with RTL, architecture, Design for Test (DFT), and other cross-functional teams across both local and global sites.

If you are looking to apply your PD expertise in a dynamic and forward-thinking environment, this is a great opportunity to explore.

What You Can Expect

• Provide technical direction, coaching, and mentoring to employees on your team and others to achieve successful project outcomes

• Perform synthesis, floor planning, place and route, timing analysis/closure, and DRC/LVS cleanup on complex logic blocks

• Develop and implement timing closure and logical ECO’s

• Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation

• Work with a variety of teams to pull in their required portion of the design, such as DFT and clock distribution teams

• Leading a small group of engineers, ensuring they are progressing, meeting milestones on schedule and quality, and providing on-time, correct deliverables

• Work with the global timing team in debugging/resolving any block level timing issues seen at full chip

• Test and maintain chip end-to-end flows, with specific focus on place and route, integration, and timing

• Interact with tool vendors to drive tool fixes and improvements in support of on-going and planned CAD activities

• Perform tool evaluations of new vendor tools and functions

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree

• 7+ years of practical experience in physical design at all levels of hierarchy with multiple ASICs/SOCs

• Strong physical design knowledge and experience, from RTL or netlist handoff to GDS tape-out

• Proficient in running chip/sub-system/partition level signoff, including physical verification (DRC and LVS), along with power integrity (EMIR)

• Experienced in leading a team of block-level engineers, coordinating at the sub-system/partition level

• Experience with partition/sub-section timing closure is a plus

• Track record of collaboration with RTL team

• Good knowledge of Verilog/VHDL is preferred

• Good understanding of digital logic and architecture

• Proficient in LINUX and shell-based scripting

• Solid knowledge and experience with TCL language

• Diligent, detail-oriented, and able to handle assignments with minimal supervision

• Must possess good communication skills, be a self-driven individual, and a good team player

• Open to candidates meeting requirements of Sr. Staff Engineer (T4)

• This role requires full-time, on-site presence at our Westborough, MA office, five days a week. If you are not currently located in the area, relocation will be necessary. Please note that remote or alternate work locations are not available for this position.

  Relocation assistance may be available for qualified candidates.

Expected Base Pay Range (USD)

165