Technical Lead, Design Verification

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell's Photonic Fabric™ team is building next-generation optical interconnect technology for the era of accelerated computing. As AI workloads scale, the bottleneck has shifted from compute to interconnect bandwidth, memory bandwidth, and memory capacity. Our Photonic Fabric delivers a tenfold improvement in performance and energy efficiency deployed as optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB) that integrate into customers' AI accelerators and GPUs.

You will play a key role in ensuring our SoCs are functionally correct by defining verification strategies, developing robust UVM environments, and driving continuous improvement of our verification infrastructure. This is a team that works on complex IP and SoC verification using industry-leading verification methodologies.

What You Can Expect

• Experience with protocols such as AMBA (AXI/AHB/APB), PCIe, Ethernet, I2C, SPI, or UART 

• Experience with ARM/processor subsystem verification, memory controllers, NoC, or cache designs 

• Working knowledge of C/C++ for reference modeling or firmware-driven verification 

• Familiarity with gate-level simulation and post-silicon validation debug 

• Experience mentoring junior verification engineers 

Education 

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 15+ years of relevant experience 

• Or Master's degree with 10+ years of experience 

• Or PhD with 8+ years of experience 

What We're Looking For

What You Can Expect 

• Develop SystemVerilog/UVM verification environments for complex SoCs, from block-level IPs through full-chip integration 

• Create detailed verification plans for block, IP, and SoC-level projects, ensuring comprehensive functional and code coverage 

• Architect UVM testbenches including stimulus generators, scoreboards, coverage models, and constrained random sequences 

• Collaborate closely with design, architecture, and software teams to manage milestones and ensure timely deliverables 

• Drive continuous improvement of verification methodologies and processes across the team 

• Build and optimize verification infrastructure regression frameworks, coverage tooling, and automation to improve efficiency 

• Lead rigorous testbench reviews with designers, architects, and software engineers to uphold verification quality 

• Coordinate with software and emulation teams to ensure first-pass tapeout success 

• Use leading edge AI tools to develop infrastructure and environments effectively and efficiently 

What We're Looking For 

• Strong proficiency in SystemVerilog with deep expertise