Principal Design Verification Engineer (Coherent Interconnect)

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Principal Design Verification Engineer you will contribute to the functional verification of System IP including coherent interconnect, caches, and dynamic memory controllers. This is an individual contributor role with technical leadership, heavily involved hands-on project execution. A strong background in Design Verification, TB architect skills, methodologies and hands-on experience with both block-level and top-level is required to be successful in this role. This position may start at a higher level depending on your knowledge and experience.

• You act as the go-to person for technical know-how and micro architecture
• You architect and build re-usable testbenches right from scratch
• You identify shortcomings of existing verification flows and proposing new solutions
• You propose and drive best practices and methodologies that can improve productivity
• You own key features and timely execution of tasks as per milestones
• You create test plans as per spec, challenge spec and testplan/code reviews
• You work with designers to resolve any spec issues
• You create verification environments, stimulus, and tests
• You collaborate with designers to verify the correctness of a design feature and resolve fails
• You develop assertions, checkers, covergroups, and Systemverilog constraints
• You debug and root cause functional fails from regressions
• You analyze code and functional coverage results and perform gap analysis
• You identify coverage exclusions and improve stimulus
• You work with SoC team to debug functional fails during IP bringup and feature execution
• You collaborate with Physical design teams, running and debugging gate-level simulations
• You work with Performance verification teams to help with co-sim TB bringup
• You bringup power-aware verification with UPF
• You help with Silicon bringup and root causing fails
• You mentor junior team members

Skills and Qualifications

• 20+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 18+ years of experience with a Master’s degree, or 16+ years of experience with a PhD
• 15+ years of professional experience in a design verification role
• Must have experience with Coherent Interconnect; Combined experience with LPDDR memory controllers is a plus
• Proficient with ARM protocols – CHI, AXI, ACElite, APB
• Expert hands-on coding skills in System Verilog, UVM
• Experience with Git version control, Unix/Perl scripting
• Good written and verbal communication skills
• Formal verification skills will be a plus

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a bi