Engineering Director, Physical Design
GoogleAbout the role
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- 15 years of experience in a role supporting architecture, micro-architecture, design, and verification initiatives.
- 10 years of experience in silicon management.
- Experience in compute or memory subsystems.
Preferred qualifications:
- 20 years of experience in design and leadership in complex ASIC or SoC programs.
- Experience with process and methodology around IP development and integration into SOCs.
- Experience working with memory suppliers on technical and operational fronts.
- Deep knowledge of Machine Learning architectures.
- Knowledge of high-performance memory controller, memory architecture definition and development, and IP hardening.
- Track record of successful product delivery and deployment.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software, and networking technologies that power all of Google's services.
As the Director, Hardware Engineering within Google's Hardware team, you will help deliver products that have a substantive impact on the Technical Infrastructure that powers Google. You will play a major role in our Tensor Processing Unit (TPU) roadmap by providing technical and management leadership for our strategic IP. In this role, you will drive complex engineering projects from the concept/planning stage through execution and closure. Establishing deep relationships with third-party IP vendors and memory suppliers will be a key measure of success.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
The US base salary range for this full-time position is $262,000-$377,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
- Design and deliver Machine Learning IP including compute and memory subsystems.
- Manage vertical IP groups with architecture, design, and verification functions.
- Define Hardware strategy and roadmap in collaboration with a broader engineering organization.
- Partner closely with other silicon functions in an IP/SOC development model.
- Engage with custom memory suppliers and third-party IP ecosystem.
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