Low Power/Reliability (EM-IR Signoff) Senior Staff Engineer

About Marvell

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

This position is with PSI signoff team part of The Compute and Custom Solutions (CCS) group at Marvell, Bangalore. This team as part of global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM’s. We are looking for strong technical leaders having Full-Chip EM/IR Analysis experience on hierarchical designs using industry standard tools.

Job Responsibilities:

As member of the CCS ASIC Design team you will have

• Opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design & Signoff
• Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff
• Opportunity to work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 5nm/7nm/12nm/14nm and more.

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Requirements:

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and at least 10 years of related professional experience.
• Demonstrated exposure to ASIC Physical implementation, Layout and Semiconductor device/process through previous work/intern experience or course work.
• Proficiency in power analysis, estimation, and optimization flow.
• Experience in debugging power mismatches in PD database
• Familiarity with running vector-based analysis and corresponding debug
• Understanding of noise and EM/IR flow
• Experience of running EM/IR Flow on Block and Top level with signoff experience of signal/power EM/IR and static and dynamic runs
• Good understanding of package parasitics modeling and bump modeling
• Leadership expereince in guiding a team for design sign-off during TO
• Expertise in Tcl and PERL.
• Experience in Physical design is preferable
• Scripting/programming using Tcl/Tk/Perl/Python/Shell
• Detail oriented, self-motivated team worker, good verbal, and written communication skills
• Strong Digital Design concepts and debugging skills

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The Perks

With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture.  We’ll give you all the tools you need to succeed so you can grow and develop with us.  For additional information on what it’s like to work at Marvell, visit our Careers page.

Your Future

Marvell provides a work environment that promotes employee growth and development.  We are searching for an individual who wants to grow with the company and will strive to improve performance.  If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.