Senior Design Verification Engineer
Hewlett Packard EnterpriseAbout the role
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
We are seeking a motivated and detail-oriented Senior Design Verification Engineer to join our team. This is an entry-level position ideal for recent graduates who are passionate about hardware design verification and eager to build a career in the semiconductor or systems engineering industry.
As a Design Verification Engineer, you will work alongside experienced engineers to verify the correctness and functionality of digital designs. You will develop testbenches, write test plans, debug failures, and contribute to improving our verification methodologies. This is an excellent opportunity to apply your academic foundation to real-world challenges in a collaborative, fast-paced environment.
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science from an accredited institution.
Coursework or academic projects in one or more of the following:
Digital logic design and computer architecture.
Hardware Description Languages (HDL) such as Verilog or VHDL.
Basic understanding of verification concepts (simulation, assertions, code coverage).
Familiarity with at least one programming or scripting language (e.g., Python, C, C++, or SystemVerilog).
Strong analytical and problem-solving skills.
Effective written and verbal communication skills.
Ability to work collaboratively in a team environment.
Preferred Qualifications
Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Academic or class projects involving networking protocols (e.g., Ethernet, TCP/IP, USB, PCIe) or communication protocols (e.g., UART, SPI, I2C, AXI, AMBA).
Hands-on experience with SystemVerilog and UVM (Universal Verification Methodology) through coursework or personal projects.
Exposure to constrained-random verification, functional coverage, and assertion-based verification techniques.
Experience with EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
Familiarity with scripting for automation (e.g., Python,
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