Senior Engineer I, System Engineering (Systems and Mechanical Engineering – Electrostatic Chuck (ESC))

<div class="content-intro"><p>&nbsp;</p> <p><strong>Step into a career with ASM, where cutting edge technology meets collaborative culture. </strong>​</p> <p>For over 55 years ASM has been ahead of what’s next, at the forefront of innovation and what’s technologically possible. With more than 4,500 ASMers representing 70 nationalities, our people and our advanced semiconductor devices are playing a crucial role in trends such as 5G, cloud computing, AI, and autonomous driving. But&nbsp;we’re more than just a tech company. We value diversity, inclusion and sustainability as we strive to make a positive impact on the world.&nbsp; Our development programs help support your growth, shaping your future and pushing the boundaries of innovation to unleash potential.&nbsp;&nbsp;</p></div><p>Reporting to the Expert System Engineering Manager, the Senior Engineer for Electrostatic Chuck (ESC) is accountable for the design, and delivery of hardware engineering solutions focused on ESC and heaters technology.</p> <p>The Engineer will be responsible for focusing on the development of highly innovative technologies over legacy solutions.</p> <h2>Key Responsibilities</h2> <ul> <li>Design and develop Johnsen-Rahbek (JR) and Coulombic-type ESC assemblies for 300mm wafer processing applications.</li> <li>Select and qualify dielectric materials (alumina, AlN, Y2O3) for ESC ceramic layers based on electrical, thermal, and chemical compatibility requirements.</li> <li>Define ESC clamping voltage, leakage current, and chucking/dechucking performance specifications.</li> <li>Characterize ESC electrical properties including volume resistivity, dielectric constant, and breakdown voltage across process temperature ranges.</li> <li>Analyze and mitigate wafer backside contamination, particle generation, and arcing risks associated with ESC operation.</li> <li>Support ESC integration with RF bias and DC chucking power supplies in plasma processing chambers.</li> <li>Design multi-zone embedded heater assemblies for uniform wafer temperature distribution across process temperatures (room temperature to 700°C+).</li> <li>Perform thermal modeling and simulation (FEA) to optimize heater layout, power density, and zone configuration.</li> <li>Develop and validate closed-loop temperature control systems including thermocouple/RTD sensor selection and PID control tuning.</li> <li>Characterize heater uniformity, ramp rates, and thermal response using wafer-level temperature mapping tools.</li> <li>Manage thermal stress and CTE mismatch between heater, ceramic, and base plate materials to ensure long-term reliability.</li> </ul> <h2>Required Qualifications</h2> <ul> <li>Master's degree or PhD