Head of Silicon Validation

About Etched

Etched is building the world’s first AI inference chip purpose-built for transformers, delivering over 10x the performance of NVIDIA GPUs. But that’s just the beginning. Our broader vision is to completely rethink the chip development lifecycle for a post-Moore world—enabling faster, more efficient custom silicon development than ever before. Backed by hundreds of millions from top investors, our team includes industry legends like Brian Loiler (who built products driving 80% of NVIDIA’s revenue), David Munday (who built Google’s TPU v1–v5 software and firmware stack), Mark Ross (former Cypress CTO), and Ajat Hukkoo (renowned Broadcom and Intel design exec). Etched is redefining the infrastructure layer for the fastest growing industry in history.

About the Role

We’re looking for a Head of Silicon Validation to lead bring-up, characterization, and margining for one of the largest and most complex AI SoCs ever built. Your team will push beyond digital abstractions to test real silicon under voltage, temperature, and frequency variation—surfacing edge cases that simulation can’t catch. This role is responsible for validating silicon robustness, uncovering failure boundaries, and closing the loop between design, DFT, ATE, and system performance. You’ll define infrastructure, lead debug efforts, and drive technical feedback into future tapeouts.

Key responsibilities

• Lead the silicon validation team responsible for bring-up, functional debug, and margin characterization of first-pass silicon

• Define and execute post-silicon validation plans across PVT (process, voltage, temperature) corners

• Develop infrastructure to collect, visualize, and analyze silicon behavior in lab and test environments

• Own voltage/frequency margining, and power/thermal stress testing

• Collaborate with ATE and DFT teams to define production test vectors, screen limits, and test escape criteria

• Debug silicon failures with a cross-layer mindset—bridging transistors, logic, firmware, and system behaviors

• Drive correlation between pre-silicon simulation, emulation, and actual silicon behavior

• Feed findings back into RTL, DFT, and architecture for next-generation design improvements

• Define and track metrics for silicon robustness, coverage, and validation completeness

• Manage team execution, hiring, mentorship, and infrastructure roadmap for world-class lab validation

You may be a good fit if you have

• 12+ years in silicon validation, post-silicon debug, or characterization of advanced-node SoCs, including 5+ years of team leadership

• Deep experience with PVT analysis, shmooing, guard-band tuning, and power/performance margin testing

• Strong debugging intuition across digital and analog failure modes, with hands-on lab experience

• Familiarity with bring-up of custom silicon, including use of JTAG, scan chains, and boundary scan

• Track record of working closely with ATE, firmware, and system engineering to root-cause test failures

• Understanding of how variation, aging, IR drop, and thermal behavior impact digital logic correctness

• Comfort working in fast-paced, high-ambiguity environments with first-silicon unpredictability

Strong candidates may also have experience with

• Experience with custom silicon bring-up at advanced nodes (5nm or below)

• Background in reliability engineering, yield optimization, or characterization of AI accelerators

• Experience validating chiplet-based designs or high-complexity SoCs with advanced packaging

• Knowledge of power integrity, clock jitter, signal integrity, or on-die monitoring infrastructure

• Exposure to DFT/DFD techniques and their interaction with post-silicon debug workflows

• Experience building lab infrastructure for automation, regression, and test data analytics

• Background in reliability engineering, yield analysis, or high-volume production ramp

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered

• Housing subsidy of $2,000/month