Vice President, CMOS Test Engineering & Test Operations

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell is seeking a Vice President to lead global CMOS Test Engineering and Test Operations, with end to end responsibility from test strategy and architecture through NPI execution and high volume manufacturing. This executive role is critical to delivering scalable, high quality, cost effective test solutions across a broad portfolio of advanced semiconductor products.
The VP will lead large, globally distributed organizations spanning test engineering, test operations, test hardware engineering, and test data infrastructure, and will serve as a senior executive interface to manufacturing partners, OSATs, and ATE suppliers.

Why This Role Matters
This role directly impacts Marvell’s ability to scale advanced silicon products with speed, quality, and cost efficiency. The Vice President will shape how Marvell brings next generation CMOS technologies into high volume manufacturing and will play a critical role in enabling long term growth across cloud, AI, networking, and custom silicon markets.

What You Can Expect

Test Engineering Strategy & Execution

• Own and drive the enterprise test engineering strategy across all CMOS product lines, ensuring consistent methodologies, high quality, and scalability from early development through production.
• Lead global teams responsible for test architecture, test program development, and test methodology, enabling efficient NPI ramps and sustained manufacturing excellence.
• Partner closely with Design, DFT, Product Engineering, and Manufacturing teams to ensure robust test coverage, testability, and alignment with product roadmaps.

Test Operations & Manufacturing Readiness

• Lead global test operations, including readiness for NPI ramps, high‑volume production support, and lifecycle management through sustain and end‑of‑life.
• Oversee organizations responsible for ATE hardware and software methods, test hardware engineering (load boards, probe cards, sockets, change kits), validation, deployment, and worldwide hardware lifecycle management.
• Ensure operational excellence across internal sites and external manufacturing partners, with a strong focus on quality, delivery, and cost.

Data, Infrastructure & Analytics

• Drive strategy and execution of enterprise test data infrastructure, enabling scalable data capture, analytics, yield learning, and executive‑level visibility.
• Champion data‑driven decision making across NPI and production, improving yield, cycle time, and manufacturing outcomes.

Cost, Quality & Ecosystem Leadership

• Own total cost of test strategy, including platform standardization, supplier strategy, and operational efficiency initiatives.
• Serve as an executive point of contact for ATE vendors, OSATs, and strategic partners, influencing roadmaps and securing scalable, competitive solutions for Marvell.

Organizational Leadership

• Lead, develop, and inspire large, multi‑site global teams; build strong leadership benches and succession pipelines.
• Establish clear accountability, operating rigor, and a culture of execution, collaboration, and continuous improvement.

What We're Looking For

• Bachelor’s degree in Electrical Engineering or related field (advanced degree preferred).
• 15+ years of experience in semiconductor test engineering and/or manufacturing test operations, including senior leadership roles.
• Demonstrated experience leading global organizations supporting NPI through high‑volume manufacturing.
• Deep familiarity with ATE platforms, manufacturing test flows, and semiconductor supply‑chain ecosystems.
• Proven ability to partner effectively across Design, DFT, Product Engineering, Manufacturing, and external partners.

Preferred

• Experience driving enterprise‑scale standardization across multiple product lines and geographies.
• Strong background in test hardware engineering, test infrastructure, and data/analytics enablement.
• Executive presence with the ability to