Performance Architecture Engineer – Workloads

We are seeking a Performance Architecture Engineer for Workload Analysis.  This position requires working knowledge of techniques and methodologies for workloads/benchmarks deployment, characterization,and analysis. The candidate will contribute to thecurrent high-performance designs providing learnings from detailed analysis of workloads/benchmarks running on MIPS RISC-V ISA based designs in simulation, emulation, and/or silicon environments. 

You will:

• Deploy workloads on various platforms for workload analysis.  
• Analyze workload characteristics and performance to identify ways to improve solution performance and efficiency by hardware and/or software improvements. 
• Profile complex workloads to identify hot-spots and devise ways to right-size the workloads for deployment and analysis on various platforms. 
• Develop methodologies and flows for workload characterization, reduction, deployment, and analysis.  
• Understand common industry and target specific benchmarks, as well as customer workloads, to help guide performance investigations.  

Ideally, you’ll have:

• MS degree in Electrical or Computer Engineering with 5+ years of practical experience or BS with 8+ years of practical experience.  
• Have current hands-on experience building, running, and analyzing workloads/benchmarks in bare-metal and operating system environments. 
• Have experience developing tools and workflows for workload analysis automation. 
• Have working knowledge of how to use functional and performance models for workload analysis. 
• Have experience with instruction tracing and common workload reduction techniques (e.g.SimPoint analysis) 
• Good knowledge of processor micro-architecture concepts. 
• Experience deploying Linux workloads on emulation and/or silicon platforms. 
• Experience working with gcc and llvm toolchains. 

A plus if you have:

• Deep experience with RISC-V CPU architectures 
• Compiler toolchain experience and understanding of software operation 
• Familiarity with the Sparta Modeling Framework, System-C, Gem5 or similar C++ framework 

Here’s what you can expect from us: At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers. 
At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave! 
More about us: MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. 
Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.