Physical Design Intern - CPU/AI Hardware

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Join a team shaping the performance of next-gen CPUs and AI/ML chips. As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating with top engineers to optimize some of the most advanced silicon in the world.&nbsp;</p> <p>This role is onsite, based out of Austin, TX or Santa Clara, CA.</p> <p>&nbsp;</p> <p><strong>Who You Are</strong></p> <ul> <li data-start="704" data-end="763">Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS</li> <li data-start="704" data-end="763">Solid understanding of logic design, VLSI, and transistor-level concepts</li> <li data-start="704" data-end="763">Familiar with PnR tools, timing analysis, and power optimization techniques</li> <li data-start="704" data-end="763">Comfortable scripting in Tcl, Perl, Shell, or Python</li> </ul> <p><strong>What We Need</strong></p> <ul> <li data-start="1007" data-end="1098">Support key physical design tasks—synthesis, floorplanning, PnR, clocking, timing closure</li> <li data-start="1007" data-end="1098">Analyze and improve design PPA (Power, Performance, Area)</li> <li data-start="1007" data-end="1098">Collaborate with front-end, PD, and architecture teams to influence early design decisions</li> <li data-start="1007" data-end="1098">Explore and implement new flows, tools, or RTL experiments to optimize designs</li> </ul> <p><strong data-start="1349" data-end="1372">What You Will Learn</strong></p> <ul> <li data-start="1375" data-end="1442">End-to-end physical design flow—from RTL handoff to final tapeout</li> <li data-start="1375" data-end="1442">Deep dive into timing, power, EM/IR, and area trade-offs</li> <li data-start="1375" data-end="1442">Industry-standard tools and techniques for modern chip development</li> <li data-start=