ASIC Design Engineer - Packet Processing & Ethernet

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.  

 

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. 

Cornelis Networks is hiring talented Sr. ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. A good candidate will have 15+ years of ASIC design experience, with 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet protocols such as TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking. 

Key Responsibilities:

• Develop microarchitecture specifications for packet processor and high-speed pipelined data path designs for host ethernet adaptors emphasizing low-latency performance. 

• Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic. 

• Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage. 

• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure. 

• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues. 

• Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems. 

Minimum Qualifications:

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field. 

• 7+ years of post-college experience in digital design with proficiency in Verilog and System Verilog. 

• Experience in RTL design for high-speed data paths or packet processing in ASICs. 

• Deep understanding of Host Ethernet adaptor architectures.  

• Familiarity with timing closure and modern physical design methodologies. 

• Proven ability in system-level debug and root cause analysis of technical issues. 

• Strong verbal and written communication skills. 

Preferred Qualifications:

• Knowledge of Ethernet architecture and networking protocols. 

• Prior experience with RTL development for Ethernet host adapters and system debug. 

• Expertise in multiple clock domain designs and asynchronous interfaces. 

• 7+ years of experience with scripting languages such as TCL, Python, or Perl. 

• Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.

Location: This is a remote position for employees residing within the United States.

We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. 

 

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentiv