Static Timing Analysis, Senior Staff Engineer

Job Title

Static Timing Analysis, Senior Staff Engineer

Job ID

16165

City

Austin

State/Province

Texas

Date Posted

10-Mar-2026

Job Category

Engineering

Job Subcategory

SOC Engineering

Hire Type

Employee

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an engineering professional with a passion for tackling complex timing challenges in advanced-node System-on-Chip (SoC) development. With deep expertise in static timing analysis, sign-off methodologies, and constraints development, you thrive in environments where precision and collaboration are paramount. You possess a proven track record of successful tapeouts at cutting-edge nodes (7nm, 5nm, 3nm), and you are comfortable navigating the intricacies of variation-aware timing, crosstalk, and clock distribution. Your technical acumen extends to scripting and tool automation, enabling you to streamline analysis and reporting workflows for efficiency and accuracy.

As a Senior Staff Engineer, you proactively engage with cross-functional teams—RTL designers, physical design specialists, and SI/PI engineers—to drive timing convergence and ensure robust, reliable silicon. Your communication skills allow you to lead timing reviews and sign-off meetings with clarity and confidence, influencing architectural decisions and advocating for best practices. You are committed to continuous learning and innovation, eager to explore new methodologies and technologies that advance the state of the art in SoC timing closure. If you are ready to make a significant impact and shape the future