Senior Process Integration Engineer

Key Responsibilities

Process Ownership & Technology Transfer

• Provide technical ownership of BiCMOS and BJT‑focused manufacturing process flows, including transferring processes from foundry to internal manufacturing site

• Execute and support tape‑out activities for transferring legacy and new semiconductor products into the Beaverton fab.

• Review and interpret source GDS, mask lists, MT‑form data, and validate against internal process flows and PDK structures.

• Ensure correct layer generation, scribe selection, die‑size matching, test‑line placement, and alignment with established flow requirements.

• Identify when new modules, process options, or flow changes are needed and work with cross‑functional integration teams to develop and enable them.

Manufacturing Support & Yield Improvement

• Lead engineering teams to investigate and resolve yield, defect, and parametric performance issues.

• Optimize manufacturing processes through design of experiments (DOE) and systematic data analysis.

• Evaluate and disposition wafers and lots based on electrical test results and inline parametric data.

• Drive Corrective and Preventative Actions (8D processes) to address root cause and prevent recurrence.

Cross‑Functional Collaboration

• Serve as a technical interface between Process Integration, Module Engineering, Manufacturing, Quality, and external foundries.

• Communicate clearly and effectively in high‑visibility situations with executive management, key customers, and auditors.

Minimum Qualifications

• 5+ years experience as a semiconductor Process Engineer or Process Integration Engineer.

• Master’s degree or above in Electrical Engineering.

• Strong technical foundation in wafer fabrication processes, including:

  • Photolithography

  • Chemical Mechanical Polishing (CMP)

  • Diffusion

  • Chemical Vapor Deposition (CVD)

  • Wet and dry etch

  • Rapid Thermal Annealing (RTA)

  • Ion implantation

  • Epitaxial growth

  • Metallization

• Demonstrated knowledge of semiconductor device physics, particularly CMOS and BJT technologies.

• Strong communication skills with the ability to remain composed, clear, and effective in challenging or diverse situations.

• Working knowledge of statistical process control (SPC) and applied statistics.

• Strong attention to detail with proven root‑cause analysis capability.

• Basic familiarity with failure analysis methodologies.

Preferred Qualifications

• Experience with foundry tape‑out flows (TSMC or similar).

• Experience with foundry NPI, including troubleshooting tape‑out and process‑transfer issues.

• Background in IC wafer fabrication engineering, semiconductor materials, manufacturing systems, and wafer electrical test.