Job Details:

Job Description: 

Your responsibilities will include, but are not limited to:

• Design, develop, test, and debug Fill components of a PDK and the related methodologies. These systems are used in process development, design automation, as well as hardware products, and in manufacturing.
• Responsibilities include capturing user requirements, writing code, automating flows, and designing end-to-end tests.
• In this position, you will be expected to be well versed in a verification language such as Calibre, Pegasus, and/or ICV.
• With these skills, you will need to be capable of providing algorithmic solutions to resolve density constraints on physical design to meet manufacturability.

The ideal candidate will provide innovative solutions that can be clearly expressed using verbal and written communication skills and would be expected to grow talent.

#DesignEnablement

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must possess a BS degree with 6+ years of experience or MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or related field, with the proven experience of 2+ years in the semiconductor industry.

Experience in the following areas:

- Design Rule Development using Calibre, or ICV, or Pegasus.
- Exposure to VLSI design and execution.
- Algorithmic development and translating rules into runsets.
- TCL, Python and Unix-Linux platform experience.
- Developing test cases to validate DRC, LVS, antenna, density and fill modules.

Preferred Qualifications:

6+ years of experience in the following:

- Exposure to layout, schematic entry using Cadence Virtuoso and/or Synopsys Custom Designer.
- Exposure to semiconductor device physics models and technology scaling.
- Familiar with industry standard CAD tools flows for digital analog design.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

Virtual US

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, Colorado, New York, Washington, California:$139,480.00-$209,760.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business