Sr Principal ASIC Design Engineer - Terawave

We are seeking ASIC/SOC Design engineers (levels including Principal, Senior Principal) who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth. 

Location: 
This role is based on site in San Diego, CA; Bay Area, CA; Austin, TX; Kent, WA. 

This role requires a highly skilled Design and Verification Engineer with extensive experience in complex SoC design, integration, and verification. The candidate will be responsible for driving end-to-end design and verification methodologies, from writing requirements and specifications to post-silicon bring-up. Strong expertise in Verilog/System Verilog, DSP structures, modem SOCs, ARM CPU integration, and interface protocols is essential, along with the ability to optimize performance and power, support back-end teams, and ensure seamless portability across FPGA and silicon environments.

Design and Verification

• Verilog/System Verilog experience in designing complex SOCs
• CDC, RDC, LINT
• Write requirements, specifications and test plans
• Optimize performance while keeping power low
• Clock gating (dynamic and static)
• Multi-voltage SOC front end design
• Formal verification
• Functional coverage, definition and collection
• Module verification
• Complex subsystem verification
• Complex SoC verification
• Co-simulation with software, integration of software build tool flow with simulation
• Gate simulation
• External IP integration
• ARM CPU single and multi-core integration with bus fabric, GIC, cache, MMU, secure boot
• AXI bus complex
• High performance DMA
• NOC integration
• DDR, PCIE, Ethernet, SPI integration
• High speed serdes integration
• DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface)
• Modem using state of the art DSP, coding, framing (phy and MAC)
• Sequenced and time bound data movement in DSP structures (time slots, time stamps etc)
• SOC top level integration using models for analog macros
• Verification using golden reference models in Matlab, SystemC or C
• Code coverage
• Timing constraints
• Support back-end teams during DFT, LEC, floorplan, STA

Post-Silicon

• Post silicon bring up

FPGA

• ASIC to/from FPGA flow

Minimum Qualifications

• BS, MS in Electrical Engineering or a related technical discipline
• 15+ years of experience
• Deep working knowledge and hands-on experience in innovative verification flows